In some types of memory, such as Flash memory, erasure and programming commands have a long execution time during which the memory is busy. Other commands, such as read commands, remain pending until the erasure or programming command is completed, and may therefore suffer long delays. Several techniques are known in the art for mitigating the long delay caused by such commands.
For example, U.S. Pat. No. 7,404,033, whose disclosure is incorporated herein by reference, describes a method for reading while writing to a single-partition Flash memory. A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient time available to perform the requested operation. If there is sufficient time available and the device manager is in an exclusive mode, the state of the memory device is checked to determine if it is currently executing an operation. If so, this operation is suspended and the requested operation is issued to the memory device. The device manager polls the memory device to determine when the requested operation has been completed. Upon completion, the interrupts are re-enabled and control of the memory device is returned to the system.
U.S. Pat. No. 7,110,301, whose disclosure is incorporated herein by reference, describes a non-volatile semiconductor memory device that includes memory blocks and an erase controller configured to control a multi-block erase operation where at least two of the memory blocks are simultaneously erased. In some embodiments, if a suspend command is received by the memory device while selected memory blocks are being erased, the erase operation ceases and another operation, such as a read operation, begins. When a resume command is received by the memory device, the erase operation resumes.
U.S. Pat. No. 6,717,852, whose disclosure is incorporated herein by reference, describes a semiconductor memory device that allows concurrent execution of a write/erase operation and a read operation.
U.S. Pat. No. 5,805,501, whose disclosure is incorporated herein by reference, describes a Flash memory device that includes a multiple-checkpoint erase suspend algorithm. A user may issue an erase suspend command anytime during an erase process. The erase procedure is suspended as fast as possible by allowing the erase procedure to be suspended at the first to occur of a plurality of checkpoints in the process.
U.S. Patent Application Publication 2012/0254515, whose disclosure is incorporated herein by reference, describes a method for suspending an erase operation performed on a group of memory cells in a Flash memory circuit. One example method includes providing to the memory circuit a command to erase the group of memory cells via a plurality of erase pulses. After applying an erase pulse, if it is determined that another operation has a priority higher than a predetermined threshold, the method suspends the erase operation, performs the other operation, and then resumes the erase operation.